DORD=MSB, MODE=USART_EXT_CLK, CPOL=IDLE_LOW, FORM=SPI_FRAME, DIPO=PAD0, DOPO=PAD0, CPHA=LEADING_EDGE
SPIS Control A
| SWRST | Software Reset |
| ENABLE | Enable |
| MODE | Operating Mode 0 (USART_EXT_CLK): USART with external clock 1 (USART_INT_CLK): USART with internal clock 2 (SPI_SLAVE): SPI in slave operation 3 (SPI_MASTER): SPI in master operation 4 (I2C_SLAVE): I2C slave operation 5 (I2C_MASTER): I2C master operation |
| RUNSTDBY | Run during Standby |
| IBON | Immediate Buffer Overflow Notification |
| DOPO | Data Out Pinout 0 (PAD0): DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 2 (PAD2): DO on PAD[3], SCK on PAD[1] and SS on PAD[2] |
| DIPO | Data In Pinout 0 (PAD0): SERCOM PAD[0] is used as data input 1 (PAD1): SERCOM PAD[1] is used as data input 2 (PAD2): SERCOM PAD[2] is used as data input 3 (PAD3): SERCOM PAD[3] is used as data input |
| FORM | Frame Format 0 (SPI_FRAME): SPI Frame 2 (SPI_FRAME_WITH_ADDR): SPI Frame with Addr |
| CPHA | Clock Phase 0 (LEADING_EDGE): The data is sampled on a leading SCK edge and changed on a trailing SCK edge 1 (TRAILING_EDGE): The data is sampled on a trailing SCK edge and changed on a leading SCK edge |
| CPOL | Clock Polarity 0 (IDLE_LOW): SCK is low when idle 1 (IDLE_HIGH): SCK is high when idle |
| DORD | Data Order 0 (MSB): MSB is transferred first 1 (LSB): LSB is transferred first |